task/01-clock-20mhz #1

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bruce merged 2 commits from task/01-clock-20mhz into main 2026-07-26 00:40:06 +00:00
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Add a BOARD_5V Makefile switch that derives F_CPU and passes -DBOARD_5V into
the build. BOARD_5V=1 (default, 5 V synchronous-buck rev): run the 20 MHz
internal oscillator undivided (MCLKCTRLB=0) and raise the BOD fuse to
BODLEVEL7 (~4.2 V), required because 20 MHz needs V_DD >= 4.5 V. BOARD_5V=0
keeps the legacy 3.3 V board building unchanged: 20 MHz osc divided to 10 MHz
and BODLEVEL2 (2.6 V). Clock divider and BOD fuse in main.c are gated on the
flag so both configs build and are functionally correct.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01Qx6PYci78VgBNLL3oDM6uq
baud_reg_for() applies the factory oscillator-error trim to the USART divisor.
The correction follows the supply RAIL, not the clock divider or F_CPU (the ÷2
prescaler is exact), so at 5 V it must use SIGROW.OSC20ERR5V instead of
OSC20ERR3V. Gate the selection on BOARD_5V and rewrite the comment block to
explain the rail-vs-clock distinction.

Also (dali_state_receiving.c, comment-only): annotate the DALI RX TCB0.CNT=73
pre-bias as a CPU-cycle-count constant. It compensates the PORT-ISR-entry +
path-to-software-enable latency, which is itself cycle-bound, so it stays valid
at 20 MHz (TCB0 counts at CLKDIV1 = F_CPU) — bench-verify, do not double.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01Qx6PYci78VgBNLL3oDM6uq
bruce merged commit ce1c589385 into main 2026-07-26 00:40:06 +00:00
bruce deleted branch task/01-clock-20mhz 2026-07-26 00:40:06 +00:00
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